AD9833 DDS signal generator: specs and pinout
A signal-generator module built on the Analog Devices AD9833, a direct digital synthesis chip that makes sine, triangle and square waves. You set frequency and phase over a 3-wire SPI interface. The output frequency is a fraction of the clock fed to MCLK.
Specs
| Spec | Value | Source |
|---|---|---|
| Supply voltage (VDD) | 2.3 V to 5.5 V | source Features; Specifications |
| Output frequency range | 0 MHz to 12.5 MHz (with a 25 MHz clock) | source Features |
| Frequency resolution | 28 bits; 0.1 Hz with a 25 MHz reference clock | source Features |
| Maximum MCLK | 25 MHz (minimum MCLK period 40 ns) | source Timing Characteristics, t1 |
| Serial interface | 3-wire SPI (FSYNC, SCLK, SDATA); SCLK period 25 ns minimum | source Features; Timing Characteristics, t4 |
| Output DAC | 10-bit; on-board 200 ohm output resistor, no external load resistor needed | source Specifications; Pin Function Descriptions (VOUT) |
| Supply current | 20 mW at 3 V; IDD up to 5.5 mA, code dependent | source Features; Specifications, IDD |
| Operating temperature | -40 C to +105 C (B version) | source Features; Specifications note |
Power
| Value | Source | |
|---|---|---|
| Supply | 2.3 V to 5.5 V on VDD; 0.1 uF and 10 uF decoupling between VDD and AGND; 100 nF on CAP/2.5V to DGND when VDD is above 2.7 V | source Specifications; Pin Function Descriptions |
| Current | Up to 5.5 mA (code dependent); about 20 mW at 3 V | source Specifications; Pin Function Descriptions |
Pinout
The pinout is the AD9833 chip's (10-lead MSOP). The module board's clock source, output buffering, header order and any amplitude control are not covered by an official document.
| Pin | Function | Voltage | Notes | Source |
|---|---|---|---|---|
| COMP (1) | DAC bias decoupling pin | Decouple the DAC bias | source Pin Function Descriptions | |
| VDD (2) | Positive power supply | 2.3 V to 5.5 V | 0.1 uF and 10 uF to AGND | source Pin Function Descriptions |
| CAP/2.5V (3) | On-board 2.5 V regulator decoupling | 100 nF to DGND; tie to VDD if VDD is 2.7 V or lower | source Pin Function Descriptions | |
| DGND (4) | Digital ground | 0 V | source Pin Function Descriptions | |
| MCLK (5) | Digital clock input | Sets output frequency scale | source Pin Function Descriptions | |
| SDATA (6) | Serial data input | 16-bit words | source Pin Function Descriptions | |
| SCLK (7) | Serial clock input | Data clocked on falling edge | source Pin Function Descriptions | |
| FSYNC (8) | Frame sync, active low | Low starts a new word | source Pin Function Descriptions | |
| AGND (9) | Analog ground | 0 V | source Pin Function Descriptions | |
| VOUT (10) | Voltage output (sine, triangle or square) | 200 ohm on-board resistor | source Pin Function Descriptions |
Build with it
Project ideas for the AD9833 DDS signal generator. Each link opens Soldr with the prompt filled in; Soldr assigns the pins, checks power and shows how to wire every part.
- A bench signal source with an ESP32 and an AD9833 module that I can view on a pocket oscilloscope: The chip runs from 2.3 V to 5.5 V so it can sit on the ESP32's 3.3 V, and SPI sets sine, triangle or square output. Check the module's own clock value before setting frequencies. Learning project.
- Rotary frequency tuner with display: The potentiometer feeds an ESP32 analog input, the sketch converts it to a 28-bit frequency word, and the OLED shows the value. Learning project.
- Filter response experiments: A swept sine through a resistor and capacitor shows how amplitude falls with frequency on the oscilloscope. Learning project; the 200 ohm output resistor means the filter resistor should be much larger.
Common mistakes
- Clocking MCLK faster than 25 MHz: the timing table gives a minimum MCLK period of 40 ns, and the 12.5 MHz output limit assumes a 25 MHz clock (source: link, Timing Characteristics)
- Forgetting the RESET bit at start-up: set RESET = 1 while initialising, then clear it; RESET = 1 puts the output at midscale (source: link, control register, D8 RESET)
- Writing a 28-bit frequency word in one write: with B28 = 1 it takes two consecutive 16-bit writes, low word then high word (source: link, control register, D13 B28)
Not covered by the official source
- Only the old Rev. A copy could be downloaded (analog.com refused automated download); Rev. G has current figures: re-check supply current, output amplitude and digital input thresholds against it.
- Output amplitude (VOUT) and digital input thresholds are not stated clearly in the maker's table; check the datasheet.
- Module board not covered.
Sources
- link (AD9833 datasheet Rev. A, Analog Devices)