74HC107 dual JK flip-flop: specs and pinout
A dual JK flip-flop chip in the 74HC family, with an individual active-low reset and negative-edge clock on each flip-flop. The figures here are from Texas Instruments' CD54HC107/CD74HC107/CD74HCT107 data sheet for the HC107 function; the maker of the part sold here is not stated, so another maker's version may differ in detail.
Specs
| Spec | Value | Source |
|---|---|---|
| Supply voltage (HC types) | 2 V to 6 V | source Operating Conditions (p.3) |
| Input voltage levels at VCC = 4.5 V | High at least 3.15 V; low at most 1.35 V | source DC Electrical Specifications (p.3) |
| Output drive | About 4 mA at VCC = 4.5 V for the specified output levels; absolute maximum 25 mA per output pin | source DC Electrical Specifications (p.3); Absolute Maximum Ratings (p.3) |
| Maximum clock frequency | 30 MHz minimum at VCC = 4.5 V (25 C); 60 MHz typical at 5 V, 15 pF load | source Prerequisite for Switching Specifications (p.5); Features (p.1) |
| Clock edge | Negative edge (high-to-low transition of CP); asynchronous reset is active low | source Description (p.1); Truth Table (p.2) |
| Package and pin count | 14 pins: PDIP and SOIC (CD74HC107E, CD74HC107M) | source Ordering Information (p.1) |
| Operating temperature | -55 C to 125 C | source Operating Conditions (p.3) |
| Absolute maximum supply voltage | -0.5 V to 7 V | source Absolute Maximum Ratings (p.3) |
Power
| Value | Source | |
|---|---|---|
| Supply | 2 V to 6 V (HC types) | source Operating Conditions; DC Electrical Specifications (p.3-4) |
| Current | Quiescent supply current 4 uA maximum at 25 C, VCC = 6 V | source Operating Conditions; DC Electrical Specifications (p.3-4) |
Pinout
This is a bare chip, not a module. The pin order is the 14-pin PDIP/SOIC pinout from Texas Instruments' CD74HC107 data sheet; pins 2 and 6 are the complementary outputs, read from the logic diagram.
| Pin | Function | Voltage | Notes | Source |
|---|---|---|---|---|
| 1J (1) | Flip-flop 1 J input | source Pinout (p.1) | ||
| 1Q (2) | Flip-flop 1 complementary output (shown with a bar on the sheet) | Logic diagram gives pin 2 as the complement of pin 3 | source Pinout; Logic Diagram (p.1-2) | |
| 1Q (3) | Flip-flop 1 output | source Pinout; Logic Diagram (p.1-2) | ||
| 1K (4) | Flip-flop 1 K input | source Pinout (p.1) | ||
| 2Q (5) | Flip-flop 2 output | source Pinout; Logic Diagram (p.1-2) | ||
| 2Q (6) | Flip-flop 2 complementary output (shown with a bar on the sheet) | source Pinout; Logic Diagram (p.1-2) | ||
| GND (7) | Ground | 0 V | source Pinout (p.1) | |
| 2J (8) | Flip-flop 2 J input | source Pinout (p.1) | ||
| 2CP (9) | Flip-flop 2 clock input | Negative-edge triggered | source Pinout (p.1) | |
| 2R (10) | Flip-flop 2 reset input | Active low | source Pinout (p.1) | |
| 2K (11) | Flip-flop 2 K input | source Pinout (p.1) | ||
| 1CP (12) | Flip-flop 1 clock input | Negative-edge triggered | source Pinout (p.1) | |
| 1R (13) | Flip-flop 1 reset input | Active low | source Pinout (p.1) | |
| VCC (14) | Supply | 2 V to 6 V | source Pinout; Operating Conditions (p.1, p.3) |
Build with it
Project ideas for the 74HC107 dual JK flip-flop. Each link opens Soldr with the prompt filled in; Soldr assigns the pins, checks power and shows how to wire every part.
- Two-stage binary counter on LEDs: J and K of both flip-flops go to 5 V so each toggles, the Uno sends slow clock pulses to 1CP, and output 1Q feeds 2CP so the second stage divides again. Both R pins go to 5 V. The Uno's 5 V is inside the 2 V to 6 V range. Each LED gets a series resistor of 1 k so the output current stays near 3 mA, below the figures the sheet tests. Learning project.
- A divide-by-four frequency divider with a 74HC107 and look at the waveforms on a pocket oscilloscope: An Uno pin outputs a square wave of about 1 kHz into 1CP, with J, K and R tied high. Each stage halves the frequency on the negative clock edge, so the oscilloscope shows the input, divide-by-2 and divide-by-4 traces. Far below the 30 MHz minimum clock limit at 4.5 V. Learning project.
- Toggle button with hardware reset: The Uno debounces the first button in software and sends one clean pulse to 1CP, so the flip-flop toggles its LED on each press (J and K high). The second button pulls 1R low through a path with a 10 k pull-up to 5 V, forcing Q low as the truth table says. A mechanical button wired straight to CP would give several clock edges per press. Learning project.
Common mistakes
- Expecting a rising-edge clock: the flip-flops change state on the high-to-low transition of CP (source: link, Description and Truth Table, p.1-2).
- Leaving R floating or low: reset is active low, so R held low forces Q low and the other output high; tie unused R and J/K inputs to a defined level (source: link, Truth Table p.2).
- Driving more than the output rating: a pin should stay under 25 mA absolute maximum and the specified output levels are for about 4 mA, so use a series resistor of 1 k or more for an LED (source: link, p.3).
Not covered by the official source
- The maker of the part sold here is not stated; figures are for TI's CD74HC107 HC types and another maker's 74HC107 (for example a 2 V to 6 V part with different timing limits) may differ.
- Pins 2 and 6 are the complementary outputs; their labels are read from the logic diagram.
- The 10 k resistor in the third idea is a suggested pull-up value, not a figure from the sheet.
Sources
- link (TI CD54HC107, CD74HC107, CD74HCT107 data sheet, SCHS139D, revised October 2003)