Raspberry Pi AI HAT+ (13 TOPS): specs
An add-on board for the Raspberry Pi 5 with a built-in Hailo neural network accelerator (Hailo-8L, 13 TOPS in this variant). It connects over the Pi 5's PCIe connector plus the GPIO header and is picked up automatically by Raspberry Pi OS and the camera software.
Specs
| Spec | Value | Source |
|---|---|---|
| Accelerator | Hailo-8L, 13 TOPS (INT8); the 26 TOPS variant uses the Hailo-8 | source Overview and Specification (pages 2-3); https://www.raspberrypi.com/documentation/accessories/ai-hat-plus.html Models |
| Host | Raspberry Pi 5 only; connects via the Pi 5 PCIe interface and the GPIO header; conforms to the Raspberry Pi HAT+ specification | source Overview, Specification and Warnings (pages 2-4) |
| PCIe link | The brief says it uses the Pi 5's PCIe Gen 3 interface; the Pi 5 connector defaults to Gen 2.0 x1 (5 GT/s), and Raspberry Pi says Gen 3.0 is not certified and may be unstable | source Raspberry Pi connector for PCIe; PCIe Gen 3.0 |
| Memory | Uses the memory on the Raspberry Pi 5 (no onboard RAM) | source Models table |
| Operating temperature | 0 C to 50 C ambient | source Specification (page 3) |
| Size | About 66 mm x 56.5 mm; the Hailo chip casing is about 17 mm x 17 mm | source Physical specifications |
| In the box | 16 mm stacking header, spacers and screws (allows fitting with the Raspberry Pi Active Cooler in place); ribbon cable | source Specification (page 3); https://www.raspberrypi.com/documentation/accessories/ai-hat-plus.html Hardware assembly |
| Software | rpicam-apps and Picamera2 use the NPU for supported post-processing; extra software and models must be installed | source How it works |
Power
| Value | Source | |
|---|---|---|
| Supply | Powered from the Raspberry Pi 5 (GPIO header and PCIe connector) | source No current or power figure in the brief or documentation read |
Pinout
We don't publish a pin table for this part: no official source we could verify gives one. Check the labels printed on your module, and see the notes below.
The HAT sits on the 40-pin header through a stacking header and links over a PCIe ribbon cable; the Raspberry Pi documents give no pin table for the HAT itself.
Build with it
Project ideas for the Raspberry Pi AI HAT+ (13 TOPS). Each link opens Soldr with the prompt filled in; Soldr assigns the pins, checks power and shows how to wire every part.
- Pet and parcel detector: The camera apps use the HAT's NPU for post-processing. The Pi 5 uses a 22-pin camera connector, so a 15-to-22-pin cable (not included) is needed. Tell any people in view that the camera is running.
- Workbench tool recogniser: Object detection runs on the 13 TOPS accelerator. This build boots from microSD because the single PCIe connector is taken by the HAT.
- Pose-estimation exercise log for yourself: Raspberry Pi lists pose estimation among the networks the 13 TOPS variant handles. Learning project, not a coaching or medical tool; only record yourself or people who agreed.
- Compact edge vision node: The HAT ships with a 16 mm stacking header so it fits over the Active Cooler, and the GPIO header stays reachable for an OLED status screen. Operating range is 0-50 C ambient.
Common mistakes
- Planning to run the AI HAT+ and an NVMe drive together: the Pi 5 has one PCIe FPC connector (Gen 2.0 x1); the AI HAT+ and the M.2 HAT+ each plug into it, and the documentation only notes that some devices enumerate behind a PCIe switch (source).
- Fitting it over an Active Cooler without the stacking header: the kit includes a 16 mm stacking header and spacers for that case (source: link, page 3).
- Assembling it with the Pi powered, or on a board other than the Pi 5: the brief says connect only via PCIe and GPIO, and the assembly steps start with the Pi disconnected from power (source: link, Hardware assembly).
Not covered by the official source
- No current or power figure is published in the brief or documentation.
- The brief says the HAT uses PCIe Gen 3 while the PCIe documentation says Gen 3 is uncertified and the default is Gen 2; both are quoted.
- 'AI HAT+ and NVMe share the PCIe connector' is derived: one FPC connector, used by both the AI HAT+ and the M.2 HAT+; PCIe-switch boards are noted as device-dependent in the documentation and were not evaluated.